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74LCX16821 Low Voltage 20-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
January 1996 Revised April 1999
74LCX16821 Low Voltage 20-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
General Description
The LCX16821 contains twenty non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX16821 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs s 2.3V-3.6V VCC specifications provided s 6.2 ns tPD max (VCC = 3.3V), 20 A ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s 24 mA output drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number 74LCX16821MEA 74LCX16821MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names OEn CLKn D0-D19 O0-O19 Description Output Enable Input (Active LOW) Clock Input Inputs Outputs
(c) 1999 Fairchild Semiconductor Corporation
DS012634.prf
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74LCX16821
Connection Diagram
Truth Tables
Inputs CLK1 OE1 H L L L Inputs CLK2 OE2 H L L L D10-D19 X L H X D0-D9 X L H X Outputs O0-O9 Z L H O0 Outputs O10-O19 Z L H O0

L or H
X

L or H
X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance O0 = Previous O0 before LOW-to-HIGH transition of Clock = LOW-to-HIGH transition
Functional Description
The LCX16821 contains twenty D-type flip-flops with 3STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 20-bit operation. The following description applies to each byte. The twenty flip-flops will store the state of their individual D inputs that meet the setup and hold time require-
ments on the LOW-to-HIGH Clock (CLK) transition. The 3STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the flip-flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LCX16821
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 -50 -50 +50 50 100 100 -65 to +150 (Note 4) Min Operating Data Retention VI VO IOH/IOL Input Voltage Output Voltage Output Current HIGH or LOW State 3-STATE VCC = 3.0V - 3.6V VCC = 2.7V - 3.0V VCC = 2.3V - 2.7V TA t/V Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V - 2.0V, VCC = 3.0V -40 0 2.0 1.5 0 0 0 Max 3.6 3.6 5.5 VCC 5.5 24 12 8 85 10 C ns/V mA Units V V V Output in 3-STATE Output in HIGH or LOW State (Note 3) VI < GND VO < GND VO > VCC Conditions Units V V V mA mA mA mA mA C
Recommended Operating Conditions
Symbol VCC Supply Voltage Parameter
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Unused pins (Inputs and I/O) must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage IOH = -100 A IOH = -8 mA IOH = -12 mA IOH = -18 mA IOH = -24 mA VOL LOW Level Output Voltage IOL = 100 A IOL = 8 mA IOL = 12 mA IOL = 16 mA IOL = 24 mA II IOZ IOFF Input Leakage Current 3-STATE Output Leakage Power-Off Leakage Current 0 VI 5.5V 0 VO 5.5V VI = VIH or VIL VI or VO = 5.5V 0 10 Conditions VCC (V) 2.3 - 2.7 2.7 - 3.6 2.3 - 2.7 2.7 - 3.6 2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 2.7 3.0 3.0 2.3 - 3.6 2.3 - 3.6 VCC - 0.2 1.8 2.2 2.4 2.2 0.2 0.6 0.4 0.4 0.55 5.0 5.0 A A A V V TA = -40C to +85C Min 1.7 2.0 0.7 0.8 Max V V Units
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74LCX16821
DC Electrical Characteristics
Symbol ICC ICC Parameter Quiescent Supply Current Increase in ICC per Input
(Continued)
TA = -40C to +85C Min Max 20 20 500 A A
Conditions VI = VCC or GND 3.6V VI, VO 5.5V (Note 5) VIH = VCC -0.6V
VCC (V) 2.3 - 3.6 2.3 - 3.6 2.3 - 3.6
Units
Note 5: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
TA = -40C to +85C, RL = 500 Symbol Parameter VCC = 3.3V 0.3V CL = 50 pF Min fMAX tPHL tPLH tPZL tPZH tPLZ tPHZ tOSHL tOSLH tS tH tW Setup Time, Dn to CLK Hold Time, Dn to CLK CLK Pulse Width 2.5 1.5 3.3 Output to Output Skew (Note 6) Output Disable Time Maximum Clock Frequency Propagation Delay CLK to On Output Enable Time 150 1.5 1.5 1.5 1.5 1.5 1.5 6.2 6.2 6.5 6.5 6.5 6.5 1.0 1.0 2.5 1.5 3.3 3.0 2.0 3.8 1.5 1.5 1.5 1.5 1.5 1.5 6.5 6.5 7.0 7.0 7.0 7.0 1.5 1.5 1.5 1.5 1.5 1.5 7.4 7.4 8.5 8.5 7.8 7.8 Max VCC = 2.7V CL = 50 pF Min Max VCC = 2.5V 0.2V CL = 30 pF Min Max MHz ns ns ns ns ns ns ns Units
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Conditions CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V CL = 50 pF, VIH = 3.3V, VIL = 0V CL = 30 pF, VIH = 2.5V, VIL = 0V VCC (V) 3.3 2.5 3.3 2.5 TA = 25C Typical 1.0 0.6 -0.8 -0.6 V V Units
Capacitance
Symbol CIN CO CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter Conditions VCC = Open, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC VCC = 3.3V, VI = 0V or VCC, f = 10 MHz Typical 7 8 20 Units pF pF pF
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74LCX16821
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC = 3.3 0.3V VCC x 2 at VCC = 2.5 0.2V GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tR = tF = 3ns) Symbol Vmi Vmo Vx Vy VCC 3.3V 0.3V 1.5V 1.5V VOL + 0.3V VOH - 0.3V 2.7V 1.5V 1.5V VOL + 0.3V VOH - 0.3V
trise and tfall
2.5V 0.2V VCC/2 VCC/2 VOL + 0.15V VOH - 0.15V
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74LCX16821
Schematic Diagram Generic for LCX Family
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74LCX16821
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A
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74LCX16821 Low Voltage 20-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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